The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device including a multi-layer metal wiring pattern.
Generally, a semiconductor device includes a device pattern layer 12 having a plurality of unit device patterns (not shown) on a semiconductor substrate 11, as shown in FIG. 1. An Inter Layer Dielectric (ILD) oxide film 13 is deposited on the device pattern layer 12. Lower metal layers 14, 15 and 16 are sequentially formed on the ILD oxide film 13. The lower metal layers 14, 15 and 16 are patterned.
An Inter Metal Dielectric (IMD) oxide film 17 is then deposited on the entire structure. A contact hole (not shown) for forming a contact plug 18 is formed within the IMD oxide film 17. Thereafter, the contact hole is filled with a conductive material to form the contact plug 18. Upper metal layers 19, 20 are sequentially formed on the entire structure.
When the contact hole is formed within the IMD oxide film 17, only the IMD oxide film 17 is to be etched. As can be seen in FIG. 1, however, a portion of the lower metal layer 16 and the lower metal layer 15 may also be etched (i.e., a punch through phenomenon may occur).
If the lower metal layer 16 is etched as described above, the contact resistance between the lower metal layers 14, 15 and 16 and the upper metal layers 19 and 20 is changed. As a result, the yield is lowered during the mass production of the semiconductor devices.
To prevent the problem described above, sufficient punch through margins can be obtained by increasing the thickness of the lower metal layer 16. In the case of highly-integrated semiconductor devices, however, there is a limit to how thick the lower metal layer 16 can be increased. In addition, the extra thickness of the lower metal layer 16 increases the amount of etching needed when the lower metal layers 14, 15 and 16 are patterned. In a subsequent deposition process of the IMD oxide film 17, the IMD oxide film 17 does not fully bury the etched portions of the lower metal layers 14, 15 and 16. Accordingly, voids may be generated.